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Q&A from Analog Devices EngineerZone: SigmaDSP/SigmaStudio and DSP discussions (17 topics).
17 topics · 74 messages
Filtered by: #mclk ✕
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Inquiry on ADAU1761 extern MCLK Clock Synchronization and CRC Verification Method
Hello Teams, In a custom project, the MCLK for the ADAU1761 is sourced from an external chip (referred to as Chip B). Since the main control chip (MCU) cannot determine the exact time when Chip B outp
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Issue with external MCLK
Dear Community, I am experiencing a weird issue with the clock settings setting up an ADAU1467. When I apply an external 24.576Mhz clock to the MCLK Pin the bitclock I see on the serial outputs is too
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MCLK issue and replicable Adau chip
Hello every , and Hello DAVE, I look into this ADIEngineerZone for long time, but this is my first time post here. I have a Bluetooth project using Adau1761, the Bluetooth chip cannot generate MCLK to
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ADAU1701 IIS input 192Khz signal to enable filter, DAC playback has noise
Specific operation description: As shown in the schematic diagram above, currently only one General 2nd filter is added, set to hpf and 60Hz corner frequency. Set the sample rate to 192K and the DSP c
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MCLK Source Select on ADAU1467 eval board
Whilst reviewing the schematic for the EVAL-ADAU1467 board, I've noticed an 0R00 resistor (R35) that continuously connects the crystal to the XTALIN/MCLK pin of the ADAU1467 DSP. Does this not comprom
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MCLKI current draw when PVDD/AVDD off (ADAU1701)
I noticed an oddity with this device. For my design, I have to turn off AVDD/PVDD in standby due to a power-hungry codec elsewhere. This keeps us in compliance with standby current. Trouble is, with P
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I2S signal frequency relation between ADAU1450 & AK4621, please verify
Hello I am running ADAU1450 in FS 96khz mode along with Codec AK4621 configured for the same sampling frequency mode. I am getting below readings MCLK 12.288 MHZ LRCLK 96 KHZ BCLK 6.14 MHZ SDATA_IN3 7
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ADAU1701 PLL modes for 45.1584 & 49.1520 MHz MCLKs?
Hi guys, hope you could help me figuring out, if a allo kali reclocker with its 45.1584 & 49.1520 MHz MCLKs is compatible to the ADAU1701 and if so, which PLL_modes to use (s. Setting the PLL mode for
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PLL Enable/Disable not working when selfbooted
adau1452 i2c selfboot Hello Community, we are having problems when trying to disable and re-enable PLL after ADAU1452 has self booted through I2C eeprom. Here is a brief description of my project: I b
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ADAU1701 DAC clock driven from PLL or MCLK ?
I have a ADAU1701 design with the MCLK driven from a dirty clock from a spdif receiver. this affects the noise floor of the DAC severely. I hoped that I could clean up the DAC clock by decreasing the
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ADAU1701 + S/PDIF in + I2Sin/out+ internal ADC/DAC + external DAC
Hi there, we are planning a small DSP board using the ADAU1701. Features should be: internal ADC (2 channel) internal DAC (4 channel) external S/PDIF receiver (maybe with transmitter to) external DAC
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Damping Resistor(s) for MCLK Distribution
The picture below shows a ADAU1401 eval board sending TDM audio to a ADAU1701 on a re-purposed prototype board. Four twisted pairs run the MCLK, BCLK, LRCLK, and TDM data between the boards. The recei
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ADAU1761 and ADAU1361 MCLK Range and PLL Range
I am looking for the lowest MCLK frequency that the ADAU1761 or ADAU1361 can operate with. I see in the spec the following: 488nsec period = 2.05MHz... Meanwhile, the front page of the datasheet shows
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MCLK rate fluctuating
Hi there, I'm running an ADAU1701 and have found that my MCLK frequency fluctuates. Specifically, in master mode, the clock doesn't stay at one frequency. This is leading to a noisy I2S output. I've t
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1701 mclk vs max instructions
For the ADAU1701, if I change the MCLK from 12.288MHz to 24.576MHz and I have a sample rate of 192kHz, does the maximum number of instructions increase from 256 to 512 instructions maximum? Audio Sign
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ADAU1702 Master Clock to drive external ADC and DAC
Hi, I'm designing a system with a ADAU1702 and better performance ADCs and DACs. Should I take the master clock from pin31 "OSCO" pass it thru a buffer/ inverter? and maybe increase a bit the 100 ohms
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Is it possible to change the frequency of MCLK while a SigmaDSP is in operation?
Is it possible to change the frequency of MCLK while a SigmaDSP is in operation? master_clock mclk frequency SigmaDSP