EngineerZone Forum

Q&A from Analog Devices EngineerZone: SigmaDSP/SigmaStudio and DSP discussions (1 topics).

1 topics · 8 messages

Filtered by: #slave+to+clockdomain ✕

ADAU1452 SDATA_OUT3 SLAVE to CLK DOMAIN 0 does not work
SigmaDSP & SigmaStudio Beni Jul 19, 2021 00:00 7 replies —

ADAU1452 ADAU1467

Hi, i have a project with an ADAU1452 where SDATA_OUT0 is configured with LRCLK and BCLK as Master. The signal is output on SDATA_OUT0. SDATA_OUT3 ist configured with LRCLK and BCLK as Slave to CLK do