ADAU1452 Port Clock Speed Capability

Hello Richard,

This has less to do with current drive capability and everything to do with PCB layout. PCB trace impedance, length or traces, and termination. The control of reflections and the timing is all important.

I suggest you read up on the theory. It is very important even to the relatively low frequencies we use in serial audio. It has everything to do with the frequency content of the edges. Here is a great place to read up on this topic.

https://www.bethesignal.com/bogatin/

The 1452 has adjustable drive strength and can drive a fairly strong signal but if you increase the drive strength then you can run into EMI radiation issues. Then if you are driving four DACs with the same signal you have four different trace lengths and controlling the reflections can become difficult. So having a clock buffer drive these parts separately can help that problem but then you can also add a bit of jitter but you can use lower drive strengths to keep EMI down. So it is all about trade-offs in the end.

Then there are some basic physics to overcome. For sending data out of the DSP to a DAC it would be best for the DSP to be the master. This is because it will send out the bit clock edge at pretty much the same exact time as the data edge. If the DSP is a slave then the DSP has to wait for the bit clock edge to "tell it" to send out the next data bit. So there is a delay internally once the clock edge is detected to then output the next bit. It is a small number but at 192kHz fs with a bitclock of 12.288MHz you have a bitclock period of ~81nS. You have half that time to get the data bit to the new level and then the time of flight for the electrons to arrive at the receiving serial port. So that is ~40nS. The default drive strength is the minimum so the MAX delay over all temperatures and all silicon skews is 35nS. So that leaves you 5nS for the signal to arrive which is not enough in most cases. So you have to use a higher drive strength. (now I should mention that this number is the worst case for the worst part and then a 6-sigma guard band is applied to come up with the number but you still need to design for this.)

So if you increase the drive strength then you get more reflections if you have a poor CPB layout with many vias to cause reflections etc. The more destinations the more reflections so you have to damp the line which slows down the edge which makes the timing worse. This is why buffers will help. This is why I mentioned that PCB layout is a huge factor when trying to run at these higher sampling rates.

In the post you quoted, they had signals that were 96kHz coming in and they wanted to run the core at 192kHz. That is wasteful and makes no sense unless there is another reason with the design that I am not aware of. This is what I was pointing out to them. If you have a 96kHz signal source there is no reason to run the DACs at 192kHz even though they can do it. You do not get any more bandwidth out of the signal. You only increase the difficulty with the PCB layout and the chance for problems.

So I need to say that the ADAU1452 does NOT have any performance problems at higher rates. It is actually quite flexible in that you can adjust the slew rate and the drive strength to give you options in your system. The timing is much better at higher drive strengths so there are no issues. Most of the variables are with the PCB implementation which is out of our hands.

Dave T

Hi David,

Thanks for the detailed reply - sorry for the late response, the system does not send e-mails to notify you that there is a response.

I am implementing a three way speaker, and the ADAU1452 is providing the LF, MF and HF outputs to 3 DAC IC's - so each port is connected to one DAC only. The fourth output if the full frequency signal to a fourth DAC.

Thanks for the reference to the website. I do have a PCB design book by Douglas Brooks - covers the areas on PCB routing techniques. I have attempted to minimise the use of vias, and where one is used, it is the lowest data rate signal/track.

I can implement the 96kHz data rate - i have 96kHz recordings, but should i purchase 192kHz recordings, then i can reprogram the DSP to increase the clock rate.

The drive of the ADAU1452 seems to be more than capable for the system design - thanks for confirming - so i will not implement the buffers.

Thanks again for the detailed reply - much appreiated.

Regards,

Richard.

Hello Richard,

Regarding the email notifications. It is an option you can setup. In the upper corner of the window I have my picture, it does not look like you have a picture, so you click there and select "Settings"

Once there you are on the Options tab. There you select to enable email notifications. Then click on the Notifications tab on the far right. In there you can select what triggers the emails. I get emails for everything so I know it works!

Glad you have been looking into the art of PCB design. It is a huge subject but some people think this is only for Gigahertz applications and not slow audio but that is not true. Even a 12MHz bit clock has very high frequency content in the edges of the signal that needs to be preserved so these concepts still apply so some extent.

Anyhow, I digress...

I have attached a basic SigmaStudio program to do much of what you need done. This should be a good starting point for you.

Enjoy the project!

Dave T

5277.ADAU1452 Basic Crossover with EQ and Limiting.zip

Hi David,

Thanks again for the reply and the project example - much appreciated.

I checked the Notifications - i thought i had set all to be sent - but have modified now - thanks.

Again, apologies for the late reply - i should be receiving notifications now.

Regards,

Richard.